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1.3 Three-Dimensional Microfabrication Background
To be classified as a true 3-D device, a structure must consist of more than just extruded 2-D patterns. It must exhibit features such as overhangs, out-of-plane joints, and enclosed cavities. The basic micromachining techniques introduced in the previous section have been used in various ways to create 3-D devices. One example is the MUMPs and SUMMiT surface micromachining processes. The structural layers associated with these processes do not allow the fabrication of high-aspect-ratio 3-D devices. However, designers rely on techniques such as hinges or polyimide joints to enable planar structures to rotate away from the substrate [20,21]. If necessary, further assembly can be accomplished by means of a probe station or through an automatic process such as solder self-assembly [22]. Unfortunately, 3-D surface micromachined devices are as mechanically compliant as their 2-D counterparts.
Although DRIE is limited to the creation of extruded 2-D patterns, other processes can be used in conjunction with DRIE to produce high-aspect-ratio 3-D devices. The combination of wafer bonding and DRIE has been explored as a way of manufacturing sensors and actuators with performance advantages over their polysilicon equivalents [11,23]. For example, a multiple-DOF capacitive sensor was constructed by using anisotropic wet etching, reactive ion etching, wafer bonding, and thin film deposition [24].
One advantage of bulk micromachining processes is the ability to create spatial 3-D devices by employing stacks of many patterned and bonded wafers. As in many polysilicon processes, oxide is used as a spacing device between silicon structures. The fabrication process is completed by using HF to dissolve the oxide. For example, a micro-scale turbine was constructed with five non-SOI wafers and sixteen masks by using aligned wafer bonding, DRIE, HF etching, and laser-assisted etching [25]. By using wafers of different thickness, considerable design variation is possible. However, the numerous alignment and bonding steps can be an obstacle to achieving high device yields.
It is no coincidence that all of the techniques reviewed to this point are batch fabrication processes, which is an essential feature of the desired 3DMEMS process. The term "batch fabrication" is taken to mean that once masks are produced for lithography, subsequent process steps fabricate all the devices on the wafer simultaneously. In general, economies of scale cause manufacturing costs to drop when hundreds or thousands of devices are fabricated simultaneously.
Many other 3-D microfabrication processes have been explored. For example, focused ion beams and lasers have been used to create overhangs and tunnels through localized chemical vapor deposition [26,27]. Laser-induced chlorine etching has been used to create cavities and tunnels in silicon [28]. Devices have also been fabricated by using electro-discharge machining [29]. Finally, 3-D microstructures have been assembled by arranging micro-blocks of silicon manually and bonding them together [30]. The disadvantage of these processes is the requirement for individual or sequential device fabrication, which increases manufacturing time and expense.
A reliable batch process for fabricating robust, true 3-D microstructures in SCS using SOI wafers has not previously been demonstrated. Consequently, a primary objective of the 3DMEMS program is to develop such a process. The use of SOI wafers should prove advantageous by providing two structural layers per wafer without requiring an additional wafer bonding step. It is a challenge to design a 3-D fabrication process that does not require individual machining, but is complex enough to create useful devices. The capabilities of this novel process will determine if it can compete with individual micromachining processes.